10+ Patents

Granted / Pending

(US / China)

10+ Technical Papers

IEEE/IET/HKIE

Digital IP

Software IP

Analog IP

Production IP

Power IP

IEEE Papers

Publications

2025
IET 2025
Analogue In-Memory Neuron Array Computing for Power-Constrained Edge CNN Applications
Nov 2025
Abstract:

This paper introduces the design of a convolutional neural network (CNN) in-memory computing accelerator neuron array, which integrates an SRAM storage architecture with charge-domain computation. In this design, weights are stored directly in 6T SRAM cells, and multiplication is implemented using XNOR logic. The resulting bit-wise products are converted into charge on integrated capacitors, which share and accumulate charges proportional to their corresponding weights. This approach creates a highly scalable analogue in-memory computing architecture that addresses the "memory-wall" bottleneck and mitigates the energy inefficiencies of traditional von Neumann systems. Tailored for edge-computing applications—such as virtual-reality and augmented-reality headsets, as well as autonomous electric vehicles—this neuron array accelerator significantly enhances the speed of image-processing algorithms while adhering to strict power constraints.

As AI algorithms and edge devices become increasingly prevalent, concerns about power consumption and environmental impact have gained prominence. While GPUs and TPUs offer impressive raw performance, their dependence on off-chip memory exacerbates the memory-wall issue, and their high power consumption and cooling demands hinder sustainable operation. Energy efficiency has therefore become a critical challenge for next-generation AI hardware. In contrast, our analogue in-memory computing solution delivers superior bandwidth and computational speed while substantially reducing energy consumption. This aligns with green computing principles and enables battery-powered or even solar-driven, self-sustaining operation in remote or mobile environments. Additionally, compared to current-domain in-memory computing approaches, the charge-domain technique offers more linear multiply-accumulate (MAC) results, enhancing accuracy and simplifying downstream signal processing.

Our accelerator operates at a 1.8 V supply, producing output voltages ranging from 0 to 1.8 V in 180 nm TSMC process. By precisely sizing capacitor ratios based on stored weights, the neuron array completes multi-bit MAC operations in just two clock cycles. Energy per MAC is reduced to approximately 0.175 pJ, achieving an overall efficiency of 5.73 TOPS/W. The analogue outputs of the neuron matrix can be digitized using a minimum 7-bit analogue-to-digital converter (ADC). The architecture supports direct computation on digital input/output streams and, with minor modifications, can process raw analogue signals from image sensors. The proposed design has been thoroughly validated through circuit-level simulations, confirming its suitability for accelerating all convolutional layers in modern CNNs.

IET 2025
Advanced On-Chip Dual-Channel Multiphase DC-DC Controller Design for High-Efficiency Power Delivery in AI Chipset Environments
Nov 2025
Abstract:

This paper presents a dual-phase on-chip DC-DC buck converter designed for power delivery in AI chipset applications. The design employs interleaved phase currents to minimize input and output ripple, reducing capacitance requirements. A dynamic current-balancing mechanism maintains phase current deviation at 9.94%, reducing component stress. Fabricated in a 0.18 μm CMOS process, the converter integrates a current-sensing amplifier, feedback network, and PWM logic. Duty cycles are modulated using a composite signal of sensed phase current and a ramp source. Operating at 700 kHz with a 12 V input and 3 V output, the converter supports load currents from 3 A to 40 A, achieving a peak efficiency of 94.58% at 10 A. Simulations indicate a 6 mV output voltage ripple and a 175 μs recovery time for a 40 A load step. Experimental results from a prototype confirm a 200 mV peak-to-peak ripple and stable regulation under dynamic loads, validating the design’s performance for AI chipset applications.

IET 2025
RISC-V Based Power Delivery Controller with Adjustable CC/CV Function for Extended Battery Lifetime in UPS and Battery-Powered Devices
Nov 2025
Abstract:

Battery-powered systems face a fundamental trade-off between fast charging and long-term battery health. This paper presents a novel approach to extend battery life using the USB Power Delivery (PD) protocol for adaptive charging, implemented on a RISC-V softcore processor in FPGA. We provide an overview of battery technologies and their charging constraints. Existing charging methods from standard constant-current/constant-voltage (CC-CV) to smart multi-stage chargers are reviewed. In this paper, an adaptive charging controller is proposed that utilizes USB PD protocol and leverages a custom 32-bit RISC-V softcore on an Artix-7 FPGA. The controller dynamically adjusts charging current and voltage based on battery temperature and state-of-charge, negotiating optimal power delivery profiles via USB PD. Experimental validation using a RISC-V-based USB PD setup demonstrates improved battery longevity, lower thermal rise, and high charging efficiency compared to conventional methods. The results infer that our adaptive PD charging strategy can significantly reduce cell stress – leading to cooler charging cycles and extended cycle life – without substantial compromise in charging time. This work illustrates a practical synergy between open-source RISC-V control and USB PD for intelligent battery management, with implications for safer and longer-lasting battery systems in portable electronics and renewable storage applications.

IET 2025
Designing an Edge AI Accelerator for Digitalized Sustainable Finance: Trading Green Bonds and ESG-Aligned Securities
Nov 2025
Abstract:

With climate change becoming a global concern, the demand for sustainable finance has never been more significant. Investors increasingly seek efficient and digitalized ESG (Environmental, Social, and Governance) investment solutions that not only generate financial returns but also promote environmental and social objectives. Achieving this requires processing vast amounts of business and industry data, enabling fund managers to gain valuable insights and make informed investment decisions. Artificial intelligence (AI) has emerged as a powerful tool for analysing financial big data, such as company reports, news sentiment, and sustainability metrics, to generate ESG scores. By integrating ESG factors into investment strategies, AI helps investors better manage risk and achieve sustainable long-term returns.

This paper presents an edge AI accelerator designed to address the computational challenges of digitalized sustainable finance applications. The proposed framework leverages field-programmable gate array (FPGA) technology to accelerate the extraction of key financial indicators, such as Relative Strength Index (RSI), Moving Average Convergence Divergence (MACD), and Stochastic Oscillator (KDJ), from real-time data streams of green bonds and ESG-aligned securities. By enabling data-driven investment strategies and low-latency trading algorithms, the proposed accelerator enhances both the efficiency and accuracy of ESG-based financial decision-making. By offloading signal processing tasks to the edge, the AI accelerator significantly improves efficiency and responsiveness in digitalized sustainable finance workflows.

The hardware-accelerated platform delivers up to 12 times faster computational speed compared to software-based approaches, enabling faster decision-making and trade execution in green bonds and ESG-aligned securities trading. The proposed edge AI accelerator represents a major advancement in fintech for sustainable finance, empowering financial institutions and asset managers to make more informed, data-driven, and ESG-aligned investment decisions. This, in turn, contributes to the transition toward a more sustainable and decarbonized economy.

IET 2025
Edge AI for Real-Time Monitoring in Industrial Environments
Nov 2025
Abstract:

This paper introduces the development of a real-time image dehazing system for industrial environments, leveraging Edge AI and deep learning algorithms, with a strong emphasis on environmental sustainability and alignment with ESG (Environmental, Social, and Governance) principles. The system utilizes an optimized deep learning model, deployed on edge devices, to analyze and monitor hazy images directly at industrial sites. By processing data locally on edge hardware, the system significantly reduces latency and minimizes energy consumption associated with cloud data transmission, thereby supporting environmental sustainability through a reduced carbon footprint.

This contributes to environmental protection by enabling immediate detection and mitigation of excessive emissions, helping to curb air pollution and combat climate change. The demonstration system is developed using Pyside6, incorporating a user-friendly interface for registration and login to facilitate operator interaction. Data security, a critical component of governance, is ensured through sqlite3 as the storage engine and Md5 encryption for secure data handling on edge devices. Additionally, a Captcha verification system is integrated to enhance user authentication, reflecting social responsibility by protecting user privacy.

By harnessing Edge AI, this system not only advances technological innovation but also aligns with ESG goals through energy-efficient processing, environmental protection, and sustainable industrial practices.

IET 2025
Hardware-Accelerated Risk Enforcement for HKEX ESG High-Frequency Trading in Power Sector Derivatives
Nov 2025
Abstract:

This paper introduces a hardware-accelerated CRC32 verification module to meet the ultra-low-latency demands of pre-trade risk management in high-frequency trading. Targeting the HKEX OCG-C binary protocol, the solution is implemented in Verilog for an Xilinx Virtex UltraScale+ FPGA deployed within an Arista 7130 Layer-1+ switch. The design architecture supports two validation modes: a comprehensive CRC recalculation and a fast differential update method optimized for incrementally modified order messages.

Post-synthesis analysis validates the high-performance characteristics of the implementation, which achieves timing closure at 250 MHz with a latency of less than 5 microseconds while consuming minimal hardware resources. Extensive functional simulations have confirmed the bit-accurate correctness of the module. However, a key finding reveals that the practical advantage of the differential update method is limited, as data mutations in real-world trading messages are typically scattered rather than localized.

This work establishes a robust framework for pre-trade risk checks by providing a deterministic, low-latency foundation for packet integrity verification. The principles demonstrated here hold significant potential for extension into other latency-sensitive domains, such as ESG-driven trading in power derivatives markets, thereby contributing to the advancement of green initiatives and the economics of carbon reduction.

IET 2025
A Programmable USB-C Fast-Charging Adapter with Dynamic Voltage/Current Regulation and Modular I2C Firmware Control
Nov 2025
Abstract:

This paper introduces a programmable USB-C fast-charging adapter prototype designed to deliver optimized power through dynamic voltage and current regulation. The system leverages a configurable power management integrated circuit (IC) that dynamically adjusts output parameters, ranging from 5 to 20 volts and 0 to 5 amps, in accordance with USB Power Delivery (USB PD) 3.1 specifications and other prevalent fast-charging protocols. This adaptability ensures seamless compatibility with a wide range of devices, from smartphones to laptops, by facilitating real-time source-sink negotiations. The prototype’s architecture is engineered to enhance power delivery efficiency, achieving a peak efficiency of 94% under dynamic load conditions, as validated through experimental testing.

The core innovation lies in the integration of a modular C++ firmware library, which employs object-oriented design patterns to abstract low-level register control via the I2C communication protocol. This abstraction simplifies the development process by providing a high-level interface for developers, reducing the complexity associated with direct hardware manipulation. The firmware is designed for cross-platform compatibility, supporting both ARM and RISC-V microcontrollers, which broadens its applicability across diverse hardware ecosystems. This flexibility makes the system particularly suitable for integration into resource-constrained environments, such as Internet of Things (IoT) devices and portable electronics, where power efficiency and adaptability are critical.

The proposed architecture addresses key scalability challenges in modern electronics by unifying adaptive hardware control with developer-centric software abstractions. By streamlining the interaction between hardware and software, the system enables rapid prototyping and deployment in energy-sensitive applications, such as wearable devices, smart home systems, and other IoT-enabled technologies. The combination of efficient power delivery, robust protocol compliance, and a modular software framework positions this prototype as a versatile solution for next-generation charging systems. This work contributes to the advancement of power management technologies by offering a scalable and efficient platform that meets the growing demands of portable and IoT ecosystems, paving the way for more sustainable and adaptable energy solutions.

IET 2025
Energy-Optimized Edge-AI Vision System with Hardware-Accelerated Intrusion Detection and Incremental Facial Recognition
Nov 2025
Abstract:

We propose an innovative energy-optimized edge-AI camera system that integrates hardware-accelerated neural networks with eco-conscious design principles, specifically tailored for intrusion detection and facial recognition tasks deployed on a low-power Neural Processing Unit (NPU)-embedded System-on-Chip (SoC), which allows for optimized inference without compromising on speed or accuracy. This approach addresses the challenges of power-hungry traditional systems by shifting processing to the edge, reducing reliance on energy-intensive cloud infrastructure and enabling more efficient, localized operations.

The setup achieves an impressive 23 frames per second (FPS) inference rate while maintaining an average power consumption of just 2.1W. This represents a significant 6.2× improvement in energy efficiency compared to cloud-based alternatives, which often involve data transmission overheads and higher operational costs. Furthermore, our design consumes 35% less power than conventional GPU-based edge devices, making it a more viable option for resource-constrained environments where energy availability is limited.

To further enhance energy efficiency, the system incorporates several advanced features. Dynamic power gating is employed to selectively deactivate unused NPU cores during idle periods, resulting in a substantial 62% reduction in standby power. This mechanism ensures that the device only consumes energy when actively processing data, extending operational lifespan and minimizing waste. Additionally, solar-aware operation modes are integrated, allowing the camera to adapt its power usage based on available renewable energy sources. This enables off-grid deployment, where the system can seamlessly interface with solar panels or other green energy solutions, promoting independence from traditional power grids and supporting sustainable installations in remote or environmentally sensitive areas.

Benchmarking evaluations highlight the system’s promising detection accuracy, ensuring reliable performance in real-world scenarios such as identifying intruders or verifying identities. These results align with targets for reducing Total Cost of Ownership (TCO) by minimizing ongoing energy demands, which in turn lowers maintenance and operational expenses over time. By optimizing hardware and software in this manner, our work illustrates the potential of edge-AI to handle complex vision tasks within tightly constrained power budgets.

IET 2025
AI-Powered Factory Monitoring with YOLO on Low-Power Edge Devices
Nov 2025
Abstract:

With the deep integration of IoT and industrial management, traditional factory monitoring systems face critical bottlenecks. Monitor cameras serve merely as passive video terminals, while advanced analytical functions such as object detection and human pose estimation rely entirely on cloud-based analysis, causing delays in real-time management and excessive energy consumption from continuous data transmission. This research develops an AI-powered factory monitoring system based on the Texas Instruments AM62A vision processor by deploying algorithms directly at the camera terminal. The system integrates YOLOX-S for real-time target detection and YOLOX-Pose for human pose estimation, enabling comprehensive monitoring capabilities.

Through systematic training, the YOLOX-S model achieved 69.0% detection accuracy (mAP50) for critical targets, including personnel and forklifts. On the AM62A EVM platform, the system achieves efficient real-time performance at 14–15 FPS with robust keypoint detection for accurate human pose analysis. The AM62A’s power consumption during inference is approximately 4.1W for single-channel processing, effectively mitigating the latency and energy issues of traditional cloud-based systems. This solution provides an expandable, low-power intelligent approach for factory monitoring with potential for broader IoT applications.

IET 2025
Green Economy and Machine Learning: Leveraging Technical Indicators for Sustainable Trading
Nov 2025
Abstract:

This research develops a comprehensive stock trading system that integrates traditional technical analysis with reinforcement learning and portfolio optimization, while emphasizing sustainable finance and environmental, social, and governance (ESG) principles. Unlike conventional algorithmic trading that prioritizes short-term gains, this system explicitly incorporates investments in green bonds and environmentally sustainable assets, aligning with socially responsible investment (SRI) goals.

The framework combines well-established indicators (KDJ, RSI, MACD) with reinforcement learning to generate adaptive trading signals. Factor analysis, guided by information coefficients, identifies statistically significant features from historical stock and ESG datasets, ensuring both accuracy and interpretability. A portfolio optimization module balances risk, return, and sustainability by filtering assets based on Conditional Value-at-Risk (CVaR), Value-at-Risk (VaR), volatility, and ESG scores. The system is implemented through an interactive dashboard with real-time visualization, customizable parameters, and automated execution.

Experimental results demonstrate an expected return of 28.79% with reduced risk (0.00337), outperforming an equally weighted portfolio, ESG benchmarks, and the S&P 500 index. The reinforcement learning agent further achieved 42.1% long-term NAV growth compared to 27.8% for a buy-and-hold market strategy. These findings show that algorithmic trading systems can be both profitable and socially responsible.

The study highlights practical considerations of data transparency, implementation, and generalizability. By relying on publicly available financial and ESG data, adopting modular and open-source implementation, and demonstrating adaptability to global markets, the proposed framework provides a flexible and scalable solution. It illustrates how AI-driven trading can contribute to a greener economy by systematically channeling capital toward sustainable investments.

2024
IET 2024
Innovative LDO Design for Enhanced Transient Response in RISC-V and Analog AI Computing Systems in Electric Vehicles
Sep 2024
ICEE 2024
Optimized Multi-Phase Buck Converter with Dynamic Current-Balancing for Low-Voltage High-Current EV-CPU Applications
Jul 2024
IEEE-ASAP 2024
An FPGA-based RISC-V Implementation with Software Support for Power Delivery Application (Submitted)
Apr 2024
IEEE-ASAP 2024
AI-FinTech: Hardware Accelerated Technical Indicator Extraction for Stock Trading, Investment Portfolio & Digital Built Assets, at Edge Devices with RISC-V CPU (Submitted)
Apr 2024
IEEE-ASAP 2024
Fast-Transient High-Output Current Low-Dropout Regulator for Electric Vehicle & RISC-V CPU (Submitted)
Apr 2024
2023
IET 2023
An AIoT-Based Power-Saving Audio Visualiser powered up by USB Type-C with 8051/RISC-V Core for the Smart Home & Electric Vehicle Applications
Sep 2023
ICEE 2023,
HKIE
An Efficient Bottom-Up Top-Down Power Integrated-Circuit Design Flow for USB-C and RISC-V-enabled Intelligent Electric Vehicle Applications
Jul 2023
2021
IEEE-EDTM
An Efficient & Programmable FPGA-Based Approach for Fast-Tuning Silicon CPU Design for Embedded Systems
Mar 2021
2020
IEEE-ICTA
An A.I.-Based Fuzzy Logic DC-DC Converter for USB Type-C
Nov 2020

Patent


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Semiconductor packaging with integrated and shielded inductors

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Reconfigurable DC-DC converter array utilizing a shared bus

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Air-Core Transformer Package with Ferrite Electro-Magnetic Interference (EMI) Shielding of Integrated-Circuit (IC) Chip

USA


17693566

Ferrite Electro-Magnetic Interference (EMI) Shield Between an Integrated-Circuit (IC) Chip and an Air-Core Inductor All Inside a Hybrid Lead-Frame Package

USA


US011206014B1

Digital Frequency Dithering For Switched - Mode Power Supplies ( Smps ) Using Triangular , Asymmetric Cubic , or Random Cubic Spread Spectrum Oscillators

USA


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Flexible Array Of DC-DC Converters Reconfigurable Using a Shared Serial Bus

USA


18584167

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USA

Trademark


50598672

"MaxSpeed" (China Trademark)

Aug 2021


59489154

"HTT" (China Trademark)

Nov 2022